Noise isolation and the elimination of complementary metal-oxide semiconductors (CMOS) latch-up are significant issues in advanced CMOS technology, radio frequency (RF) CMOS, and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology. Latch-up conditions typically occur within peripheral circuits or internal circuits, within one circuit (intra-circuit), or between multiple circuits (inter-circuit). In one such example, latch-up occurs when a PNPN structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e., forming an S-Type I-V (current/voltage) characteristic).
In particular, latch-up is known to be initiated by an equivalent circuit of a cross-coupled PNP and NPN transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second device (“regenerative feedback”). These PNP and NPN elements can be any diffusions or implanted regions of other circuit elements (e.g., p-channel MOSFETs, n-channel MOSFETs, resistors, etc.) or actual pnp and npn bipolar transistors. In CMOS structures, the PNPN structure can be formed with a p-diffusion in a N-well, and a n-diffusion in a p-substrate (“parasitic PNPN”). In this case, the well and substrate regions are inherently involved in the latch-up current exchange between regions in the device.
The condition for triggering a latch-up is a function of the current gain of the PNP and NPN transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular PNPN structure to latch-up is a function of a same combination of spacing (e.g., base width of the NPN and base width of the PNP), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Latch-up can also occur as a result of the interaction of an electrostatic discharge (ESD) device, the input/output (I/O) off-chip driver and adjacent circuitry initiated in the substrate from overshoot and undershoot phenomena. These factors can be generated by CMOS off-chip driver circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate, and simultaneous switching of circuitry where overshoot or undershoot injection occurs may lead to both noise injection and latch-up conditions. Also, supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can be present, contributing to noise injection into the substrate and latch-up.
With the scaling of standard CMOS technology, the spacing of the p+/n+ space decreases, leading to a lower trigger condition and the onset of CMOS latch-up. With the scaling of the shallow trench isolation (STI) for aspect ratio, the vulnerability of CMOS technology to latch-up has increased. Vertical scaling of the wells, and lower N-well and P-well implant doses also has increased the lateral parasitic bipolar current gains, leading to lower latch-up robustness.
With the transition from p+ substrates to low doped p-substrates, the latch-up robustness has continued to decrease. Also, the effectiveness of N-wells as guard ring structures may reduce internal and external latch-up problems. But, with mixed signal applications and radio frequency (RF) chips, a higher concern for noise reduction has lead to the continued lowering of the substrate doping concentration. This continues to lead to lower latch-up immunity in mixed signal applications and RF technologies.
Latch-up also can occur from voltage or current pulses that occur on the power supply lines. Transient pulses on power rails (e.g., substrate or wells) can trigger latch-up processes. Latch-up can also occur from a stimulus to the well or substrate external to the region of a thyristor structure from minority carriers.
Latch-up can be initiated from internal or external stimulus, and is known to occur from single event upsets (SEU), which can include terrestrial emissions from nuclear processes, and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, neutron, and gamma events, as well as a number of particles that enter the earth atmosphere. Terrestrial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latch-up in semiconductors.
Latch-up can lead to failure of space applications triggered by cosmic rays, heavy ions, proton and neutron events. The higher the latch-up margin in military and outer space applications, the higher the vulnerability to single even upset (SEU) initiated latch-up.
Smart power technology today consists of high voltage CMOS (HVCMOS) integrated with low voltage CMOS (LVCMOS). In these technologies, the HVCMOS sectors utilize lateral diffused MOS (LDMOS) transistors. Applications voltages vary with the product. In the 80V to 120V application range, products consist of automotive, telecommunication, and power supplies. In the 20V to 80V application range, products consist of automotive displays, inkjet printers, DC/DC converters, to controllers. Below 20V application voltages, products consist of controllers, cell phones to standard low voltage electronics. System-on-chip integration can include a mixture of high voltage CMOS, digital, and analog circuitry; these systems can include voltage regulators, interface networks, digital-to-analog converters, analog-to-digital converters, current references, oscillators, current references, filters, to power management supervisors. Crosstalk, noise and latch-up are common concerns in these products.
In the semiconductor manufacturing of LDMOS transistors, there are two types of transistors typically constructed. For medium voltage (MV) applications, the lateral diffused drain structures are placed under the MOSFET gate for the MOSFET source and drain. In the high voltage (HV) applications, a high voltage LDMOS transistors, isolation (LOCOS or shallow trench isolation (STI)) is placed under the MOSFET gate drain region.
To apply high voltage to the LDMOS transistors, many uniquely defined implants exist for the LDMOS transistor. For LDMOS technology, deep diffused wells are used for the LDMOS transistor. This deep diffused well implant is unique to the LDMOS transistor. In the section of the LDMOS transistors, lower doped “body” implants are formed for the p- and n-region. These P-body and N-body implants are unique to the LDMOS transistor. In the LDMOS drain regions, non-self aligned implants are used. In addition, in the case of the high voltage LDMOS transistor, the drain region extends under the isolation structure.
In the production of advanced low voltage CMOS (LVCMOS) technology on the same substrate as high voltage LDMOS technology, the current injection from LDMOS or the high voltage sector of a mixed voltage chip can be significant.
During inductive load dumps, the large area LDMOS transistor can discharge electrons into the substrate of a SOC product. Electron injection into the substrate can lead to disruption and triggering of the low voltage CMOS (LVCMOS) logic circuitry. As a result, it is desirable to have LVCMOS logic circuitry that is latch-up immune. Hence, it is desirable to provide latch-up robust low voltage CMOS technology in a mixed voltage application.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.